1. Field of the Invention
The invention relates to a semiconductor device and a method for testing the semiconductor device.
2. Description of the Related Art
A configuration in which a vertical type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for an output stage, a horizontal type MOSFET for a control circuit, and a protection element which protects these MOSFETs etc. from surge are formed on one and the same semiconductor chip is well known as the configuration of a power IC (Integrated Circuit). For example, a vertical type diode is used as a protection element of such a power IC. The case where a vertical type diode is used as the structure of a protection element of a semiconductor device according to the background art will be described by way of example. FIGS. 6A and 6B are explanatory views showing the structure of the semiconductor device according to the background art. A planar layout of a protection element 100 according to the background art is shown in FIG. 6A. A sectional structure of the protection element 100 along a cutting plane line Z-Z′ of FIG. 6A is shown in FIG. 6B.
As shown in FIGS. 6A and 6B, the background-art protection element 100 is a vertical type diode in which a p− type anode region 102 is provided on a front surface side of an n− type semiconductor substrate (semiconductor chip) serving as an n− type drift layer 101 and an n+ type cathode layer 108 is provided on a back surface side of the n− type semiconductor substrate (semiconductor chip). A p++ type contact region 103 serving as a contact (electric contact portion) with an anode electrode 104 is selectively provided in the vicinity of the center of the p− type anode region 102 inside the p− type anode region 102. The n+ type cathode layer 108 is electrically connected to a power supply voltage terminal (hereinafter referred to as Vcc terminal) through a cathode electrode 109. The p− type anode region 102 is electrically connected to a GND pad (ground terminal) 107 through the p++ type contact region 103, the anode electrode 104 and a wiring layer 106. Any other element (an output stage, a control circuit, etc.) than the protection element 100, which is formed on one and the same semiconductor substrate as the protection element 100, is not shown in FIGS. 6A and 6B. The anode electrode 104 and an interlayer dielectric 105 are not shown in FIG. 6A.
When surge applies to a semiconductor device provided with such a background-art protection element 100 through the Vcc terminal, a reserve voltage is applied to a pn junction 111 between the p− type anode region 102 and the n− type drift layer 101 so that a depletion layer 112 is spread from the pn junction 111. When the reverse voltage applied to the pn junction 111 exceeds a predetermined voltage (breakdown voltage) larger than a potential difference (diffusion potential) applied between opposite ends of the depletion layer 12, a surge current flows from the n+ type cathode layer 108 into the GND pad 107 via the n− type drift layer 101, the p− type anode region 102, the p++ type contact region 103, the anode electrode 104 and the wiring layer 106. The protection element 100 is set to break down at a reverse voltage (withstand voltage) lower than the withstand voltage of any other device than the protection element 100, which is formed on one and the same semiconductor substrate as the protection element 100, so that the protection element 100 can protect the other device from the surge. The reference numeral 113 designates a place to which an electric field is apt to be concentrated to thereby lead to occurrence of breakdown.
The following device has been proposed as the semiconductor device provided with the protection element. An n-type semiconductor substrate is divided into an MOSFET region and a guard ring region. A p-type well region is formed in each of the MOSFET region and the guard ring region or at least in the guard ring region. An impurity profile of the p-type well region and an upward diffusion profile of impurities from the n+ type substrate make contact deep enough to hide an impurity profile of an n-type epitaxial layer so that a pn junction diode can be formed. A reverse breakdown voltage of the pn junction diode is set to be higher than a normal operating voltage and lower than the withstand voltage of a semiconductor element (e.g. see JP-A-3-049257 (from line 18 of lower right column in p. 2 to line 4 of upper left column in p. 3, FIG. 1)).
In addition, as another device, a semiconductor device has been proposed as follows (e.g. see JP-A-2010-287909). The semiconductor device is provided with a transistor and a diode which are formed on one and the same substrate and connected in parallel. In the semiconductor device, resistance during a breakdown operation of the diode is made lower than resistance during a breakdown operation of the transistor and a secondary breakdown current of the diode is made higher than a secondary breakdown current of the transistor. In addition, as another device, a device has been proposed as follows (e.g. see JP-A-2003-338604). In the device, a front surface electrode of a vertical type bipolar transistor and a drain electrode of a horizontal type MOSFET are electrically connected by metal electrode wiring. When a high ESD (Electro-Static Discharge) voltage or a high surge voltage is applied, the device absorbs the ESD and surge energy by an operation of the vertical type bipolar transistor and limits the voltage to be not higher than the breakdown voltage of the horizontal type MOSFET which may lead to breakdown.
In addition, as another device, a device has been proposed as follows. An ESD protection circuit has an MISFET and a parasitic bipolar transistor whose base is connected to a high level-side power supply terminal is formed between a channel body of the MISFET and a data input/output terminal. In a normal operating condition in which a positive power supply voltage is given to the high level-side power supply terminal, the parasitic bipolar transistor maintains OFF and the high level-side power supply terminal is open. In an ESD test in which a positive voltage is given to the data input/output terminal, the parasitic bipolar transistor operates (e.g., see JP-A-2003-078021 (paragraph [0029], FIG. 1)). In JP-A-2003-078021, the withstand voltage of the protection element is changed between the normal operating time and the ESD test time.
Assume that a screening test is performed on the aforementioned power IC provided with the background-art protection element to remove a product in which initial failure occurs in another device than the protection element by applying a voltage higher than an operating voltage of the product. In this case, there is a fear that the following problem may arise. For example, the horizontal type MOSFET is formed for the control circuit and on one and the same semiconductor substrate as the protection element. When it is regarded as important to protect the horizontal type MOSFET, the withstand voltage of the vertical type diode constituting the protection element is set to be lower than the withstand voltage of the horizontal type MOSFET. Therefore, when a voltage higher than the operating voltage of the product is applied in the screening test, there is a fear that a large current may flow into the protection element to generate dielectric breakdown etc. to thereby lead to breakdown of the protection element itself. Also in the case where the withstand voltage of the protection element is changed in accordance with the circumstances as in JP-A-2003-078021, there is a fear that the protection element itself may break down because the power IC is high in voltage and large in current.
In order to solve the aforementioned problems inherent in the background art, an object of the invention is to provide a semiconductor device and a method for testing the semiconductor device, in which a protection element can be prevented from breaking down and initial failure of a device formed on one and the same semiconductor substrate as the protection element can be detected accurately.